driveAtlas: make ZimaBoard front-panel connectors recognisable
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The four front ports were identical 2-char stubs under one lumped
"GbE/USB" label, so they read as anonymous blobs. Draw them as the
hardware actually is and give each connector type its own silhouette:

  RJ45   ██▄██   solid jack with a notch cut into the top centre (latch slot)
  USB-A  █▀▀▀█   side walls plus a tongue bar filling the upper half
  mDP    ╱██╲    chamfered slot
  DC     (█)     round barrel with a centre pin

The 2x GbE and 2x USB now share ONE housing with the ethernet row sitting
directly on top of the USB row and no divider between them, matching the
physical stacked connector module. Each jack stays one row tall by using
half-block glyphs to get two vertical pixels per cell. GbE and USB get
separate labels; mDP and DC 12V sit beneath their own connectors.

Front-face height HC grows 3 -> 5 for the room. Knock-on: HC feeds FB,
which decides where the left side face stops being a vertical edge, so the
PCIe row now lands on the last vertical row and its card edge makes a real
T-junction into the chassis (▐▓▓┤) instead of floating. HC and the PCIe row
are therefore coupled if this is tuned further.

Still a fixed 66-column canvas, identical display width on every line in
monochrome and colour, SAFE width-1 glyphs only.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
2026-07-20 02:58:04 -04:00
co-authored by Claude Opus 4.8
parent 6a26feb9e9
commit a55fa85875
+27 -11
View File
@@ -1349,7 +1349,7 @@ generate_zimaboard_layout() {
local S=5 Wi=44 FL=16 # oblique depth, front interior width, front-left col
local BL=$((FL-S)) FR=$((FL+Wi+1))
local BR=$((FR-S)) # NB: separate statement; FR is not visible in its own `local`
local R0=2 HC=3 FE FB LEG HEIGHT
local R0=2 HC=5 FE FB LEG HEIGHT
FE=$((R0+S)); FB=$((FE+HC+1)); LEG=$((FB+3)); HEIGHT=$((LEG+6))
# dual grid: Gc = glyphs, Gk = per-cell colour key ('.' = default)
@@ -1430,19 +1430,35 @@ generate_zimaboard_layout() {
_zp $((FE-2)) $((FL+2)) '┌─────┐' D
_zp $((FE-1)) $((FL+2)) '└─────┘' D
# --- two-tier front I/O: mDP | [GbE over USB] | DC --------------------
local cx=$((FL + Wi/2 - 1))
_zp $((FE+1)) $((cx-2)) '▐▌' C ; _zp $((FE+1)) $((cx+1)) '▐▌' C # upper: 2x 1GbE
_zp $((FE+2)) $((cx-2)) '▐▌' B ; _zp $((FE+2)) $((cx+1)) '▐▌' B # lower: 2x USB 3.0
_zp $((FE+2)) $((FL+3)) '▐▌' S # mDP (left)
_zp $((FE+2)) $((FR-5)) '▐▌' S # DC (right)
_zp $((FE+3)) $((FL+3)) 'mDP' D
_zp $((FE+3)) $((cx-3)) 'GbE/USB' D
_zp $((FE+3)) $((FR-7)) 'DC 12V' D
# --- front I/O ---------------------------------------------------------
# Centre: ONE shared housing with 2x RJ45 sitting directly on top of 2x USB.
# RJ45 ██▄██ solid jack, notch cut into the top centre = latch slot
# USB-A █▀▀▀█ side walls + tongue bar filling the upper half
local MX=32
_zp $((FE+1)) "$MX" '┌─────┬─────┐' H
_zp $((FE+2)) "$MX" '│' H
_zp $((FE+2)) $((MX+1)) '██▄██' C
_zp $((FE+2)) $((MX+6)) '│' H
_zp $((FE+2)) $((MX+7)) '██▄██' C
_zp $((FE+2)) $((MX+12)) '│' H
_zp $((FE+3)) "$MX" '│' H
_zp $((FE+3)) $((MX+1)) '█▀▀▀█' B
_zp $((FE+3)) $((MX+6)) '│' H
_zp $((FE+3)) $((MX+7)) '█▀▀▀█' B
_zp $((FE+3)) $((MX+12)) '│' H
_zp $((FE+4)) "$MX" '└─────┴─────┘' H
_zp $((FE+2)) $((MX-5)) 'GbE' D
_zp $((FE+3)) $((MX-5)) 'USB' D
# Mini-DisplayPort (left, lower tier): chamfered slot, not a plain box
_zp $((FE+3)) 20 '╱██╲' S
_zp $((FE+4)) 20 'mDP' D
# DC 12V barrel jack (right, lower tier): round housing + centre pin
_zp $((FE+3)) 52 '(█)' S
_zp $((FE+4)) 50 'DC 12V' D
# --- open-ended PCIe x4 card edge out the LEFT side --------------------
_zp $((FE+1)) 0 'PCIe x4 ' D
_zp $((FE+1)) 8 '▐▓▓▓▌' C
_zp $((FE+1)) 8 '▐▓▓' C
# --- rubber feet -------------------------------------------------------
_zp $((FB+1)) $((FL+1)) '╹' D